Sixteen copper layers, eight reference planes, and zero room for guesswork. This is the working reference for engineers building dense, high-speed and high-power boards — stackup logic, controlled impedance, material data, manufacturing rules and what actually drives cost. When your design is ready, the 16 layer PCB fabrication service at PCBSync builds it to spec.
Pick a construction recipe, then hover or tap any copper, core or prepreg layer to read its material, thickness, dielectric constant and role. Total thickness and copper balance recompute live — the way a real stackup gets negotiated with a fab.
First-order single-ended and differential impedance for the two geometries you meet most on a 16 layer PCB: an outer microstrip and an inner stripline. Drag the sliders and watch Z₀ move.
First-order estimates (IPC-2141 style). Real 16 layer PCB impedance depends on etch trapezoid, resin content, glass-weave and copper roughness — confirm the final stackup with your fabricator's field-solver before sign-off.
The difference between a board that works first pass and one that comes back for a respin usually lives in the stackup. These are the decisions to make before you route a single trace.
Give each of the eight signal layers an adjacent solid reference plane so return current has a tight, continuous path. This is the whole reason to spend layers.
Mirror copper and dielectric about the centre line. An unbalanced 16 layer PCB warps during lamination and reflow — symmetry controls bow and twist.
Route differential pairs over a single uninterrupted plane. Never let a pair cross a plane split — the return current can't follow and you radiate.
Thinner prepreg between signal and plane lowers and stabilises impedance, and shrinks loop area. Trade it against drill aspect ratio.
Place ground vias near every layer transition and around the board edge. Reference handoff between planes is where 16-layer boards quietly fail EMC.
Dedicate full or split planes to the main rails. Solid power-ground pairs form natural decoupling capacitance you get for free.
For multi-Gbps nets, choose flat/spread-glass prepreg or rotate the artwork to avoid fibre-weave skew between P and N.
On through-via signal transitions, back-drill the unused barrel. Resonant stubs on a thick 16 layer PCB wreck high-speed eyes.
Even copper distribution helps etch and lamination uniformity. Add thieving copper to sparse layers to keep the stack flat.
Send your target stackup early. Available cores, prepregs and impedance tolerances differ by shop — lock the build before layout, not after.
A 16 layer PCB is only as good as what it's built from. These are the building blocks and the numbers that decide thickness, loss and impedance.
| Building block | What it is | Typical values | Decides |
|---|---|---|---|
| Core | Cured glass-epoxy with copper bonded on both faces | 0.075 – 0.25 mm · ½/½ – 1/1 oz | Inner layer pairs, rigidity |
| Prepreg | B-stage glass-resin sheets (1080 / 2116 / 7628…) that bond cores | 0.075 – 0.20 mm | Layer-to-layer spacing, Z₀ |
| Copper | Foil weight per layer | 0.5 oz (17.5 µm) → 2 oz (70 µm) | Current, trace/space, thickness |
| Std FR-4 | Mid-Tg glass-epoxy laminate | Dk ≈ 4.2–4.5 · Df ≈ 0.02 | General-purpose, lowest cost |
| High-speed | Low-Df laminate (Megtron, Isola, Tachyon class) | Dk ≈ 3.0–3.7 · Df ≈ 0.002–0.005 | Multi-Gbps loss budget |
| Finish | Surface plating on exposed copper | ENIG · HASL · OSP · hard gold | Solderability, edge connectors |
Two 16 layer PCBs can differ by a millimetre. Thin cores and prepreg with ½-oz copper give a slim 1.6 mm board; thick cores, 2-oz planes and extra resin push past 3 mm.
Dk sets impedance and delay; Df sets dielectric loss. On long, fast nets a high-Df FR-4 closes the eye — that's when low-loss laminate earns its premium.
Heavier copper carries more current and sinks more heat, but needs wider trace/space and adds height. Most 16-layer signal layers run ½ oz; power planes run 1–2 oz.
More layers means more lamination cycles, tighter registration and harder drilling. Knowing the process limits keeps your design manufacturable — and affordable.
Sixteen layers are aligned and pressed under heat and pressure. Layer-to-layer registration drifts with every cycle, so annular rings and pad sizes need margin. Sequential builds (for buried vias) add press cycles and cost.
Through, blind, buried, microvia and back-drilled — each unlocks routing but costs money and reliability margin. Keep the through-via aspect ratio at or below 10:1; a 2 mm board wants ≥0.20 mm drills.
A thick stack with small holes is hard to plate evenly. High aspect ratios risk voids and thin barrels. Balance finished thickness against your smallest required via.
Controlled-impedance lines are built to a measured stackup and verified on a test coupon. Standard tolerance is ±10%; ±5% is achievable but tightens material and process windows.
A 16 layer PCB isn't priced by a single number. These are the levers — pull the cheap ones first.
High-speed laminates can cost several times standard FR-4.
Each sequential lamination + laser-drill pass adds process and yield cost.
±5% needs premium materials, test coupons and lower yield.
2 oz+ planes raise material, etch difficulty and thickness.
One drill pass, no sequential build — the cheapest interconnect.
Right-size the board to the panel; less scrap, lower unit price.
OSP or HASL over hard gold where edge contacts aren't needed.
±10% impedance and Class 2 where the application allows.
When eight or twelve layers run out of routing channels, reference planes or power integrity, sixteen is the next stop.
High pin-count CPUs, DDR5, PCIe Gen5/6 and dense BGAs need every routing layer and a tight power-delivery network.
Switches, line cards and optical modules push multi-lane SerDes that demand low-loss material and clean references.
Mixed-signal radios and phased arrays use the layer budget to isolate RF, digital and power domains.
Avionics and radar payloads value reliability, controlled impedance and density inside a fixed mechanical envelope.
Imaging, instrumentation and motion control combine sensitive analog with switching power on one board.
Domain controllers, radar and compute modules need density and signal integrity that thinner stacks can't hold.
You've got the layer plan, the impedance and the material call. PCBSync turns it into a real, tested board — controlled impedance, advanced vias and high-layer-count expertise included.